<b> Ammar Abusham and Patrick McGoff </b> You’re an experienced PCB Designer using a good CAD flow. So why is it that what appears to be a good design to you and your layout tool always seems to raise a bunch of questions with your fabricator? Well, the fabricator sees things differently than you. If you are like most designers, you are very much focused on designing a PCB to the electrical and form-factor specifications. And, of course, you take pride in how clean your design looks. Your fabricator, on the other hand, is mostly paying attention to those aspects of your design which affect yield, costs, and delivery. To avoid any unpleasant surprises in these areas, it might make sense to put yourself in your fabricator’s shoes for a moment and see some of the checking they will perform on your design data prior to committing it to fabrication. To do this, we’re going to step through a typical PCB fabrication process and identify where Design for Manufacturability (DfM) issues are likely to show up and what the fabricator is looking for. Once you are aware of some of the areas where your design might require correction by the fabricator to achieve higher yields, you can implement them as you perform your design, rather than waiting for them to be discovered by the fabricator. But these rules and best practices are extensive. As a result, many designers are using DfM tools during their design process to perform these extensive checks. This way they can be assured that their design will reach target volume production levels quickly and not require major redesign. <b> The PCB Bare Board Fabrication Process </b> Let’s begin with an overview of the PCB fabrication process, as illustrated in Figure 1. We will use conventional multilayer boards as our example, but we will identify issues specific to microvia technology as well. On multi-layer PCBs, the inner layers have to be processed first, and then laminated together for outer layer processing. Once that is completed, there are several steps we are calling auxiliary processes, such as soldermask application, that have to be performed. The fabricator will then need to de-panel the PCBs and finish with test and inspection. Let’s step through this process and outline just a few of the important rules that will determine if the design can be fabricated at high yields. Keep in mind that there are actually more than 270 of these rules that could be implemented and checked. <b> Inner layer Processing </b> Within the inner layer processing stage, the first step is dry-film preparation and innerlayer coating. At this stage, the copper foil Is coated with a thin photoresist film. The inner layers will then be placed into the imaging system and both sides exposed, either with a conventional film plotter or a laser direct imaging system. They are then developed so that the unexposed photoresist is washed away. The fabricator will then etch the unprotected copper away and the protective coating on the circuits will be stripped. A common check at this point is to determine if a pad and a circuit are too close (Figure 2) and may bridge during imaging, etching, plating, or soldering and result in a short circuit. One reason why this may happen is all fabricators have to add a global etch compensation to the circuitry so that the copper features end up as designed after the etch process. Furthermore, the amount they grow the copper features will depend on what weight copper the design calls for. A design utilizing half-ounce copper will require much less etch compensation than one that calls for two-ounce copper. In applying the etch compensation, the fabricator runs the risk that they will have made the spacing between two circuits too close, and may have created an opportunity for a short. Another common inner-layer issue is with floating planes. Floating planes are areas of copper often used as reference planes that have become disconnected. Locating these areas minimizes the likelihood of a critical net losing its reference plane, or even worse, losing an electrical connection and creating an open net. These issues are most frequently seen on negative planes because of how they are displayed and output by CAD tools, but they do occur on positive planes as well. The opposite can also occur. When spacing between planes is compromised, shorts can occur between different voltage sources or between power and ground, resulting in non-functional boards. Or, we can have insufficient connection of a plated-through hole to a plane if it is not completed within the desired plane area. This can be missed by the CAD tool as electrically it shows it is still connected. When this hole is plated, it will not have a full connection to the plane, and therefore, is subject to failure. The DfM rule values can be set as a percentage of overlap to the plane required to assure a solid connection. Another common problem is insufficient thermal connection. Since the purpose of thermals is to concentrate heat into the barrel of the via for proper plating, the thermal connections to the plane must be sufficient for this heat distribution. When you have instances where all four spokes are reduced to a very small connection to the plane, there is a real risk this design will fail in the field as these vias will have poor plating within them. <b> Lamination of Layers </b> Moving into the lamination process, the inner layers are then treated with either a brown or black oxide to inhibit corrosion and provide for proper adhesion during lamination. In the “booking” process, the fabricator is laying up all the materials that will constitute the full PCB. Panels are pinned and then inner layer cores, prepreg layers, and finally the copper foils for the outer layers are stacked-up according to the recipe. Fabricators often stack up to four panels in one “book” at a time in the lamination press for greater efficiencies. The panels are placed between two metal plates in the press where pressure and heat are applied for several hours. You will want to review the copper distribution of your design to identify its potential for warping once laminated. Ideally, all layers will have a good distribution of copper throughout the design. With thincore PCBs, this is even more critical. Additionally, the fabricator is going to pay close attention to this copper distribution on outer layers for plating purposes. Poor copper distribution will make the plating process very difficult to achieve consistent quality. As you can see in the copper distribution shown in Figure 3, red represents high density areas of copper, while areas that lack copper are colored blue. This information, along with a copper versus noncopper percentage, helps the fabricator determine and apply pattern fills to evenly distribute the copper as necessary for optimum plating. Another important consideration in the lamination process is drilling. You might think, “How hard can it be to accurately drill a hole?” Well, the fact is it can be quite difficult. In addition to the material registration tolerances on a multilayer board, the layers move in a non-linear manner when put in the lamination press. So vias that aligned well prior to lamination may be marginally aligned after lamination.On top of that, often times a fabricator will drill multiple PCBs stacked together for operational savings and the opportunity for drill breakout becomes a real possibility. For this reason, minimum annular rings must be checked. Furthermore, the annular ring that is required will vary depending on whether the via is mechanically drilled or laser drilled. Mechanical drill bits always bend some as they are penetrating copper layers. <b> How a Fabricator Looks at Your Design </b> For very dense designs, designers strive for the smallest annular ring possible, as less space is taken by the pad or via and more space can be dedicated to routing the traces. However, to take the annular ring constraint lower can have a greater impact on the cost and yield when it comes to fabricating the PCB. So there are trade-offs involved and DfM provides the designer with the awareness so that they can control the trade-off decision. If your design incorporates microvias, fabricators will want to know the depth to which a microvia, or a combination of overlapping microvias, penetrates the layer stack-up as that can affect board yield. The greater the number of layers penetrated by overlapping vias, the more prone the microvia is to hole fracture. <b> Outer Layer Processing </b> Next, the laminated panel is ready for outer-layer processing. Similar to inner-layer processing, the panel will have photoresist film applied to each side. The panels are then imaged, again, with either film or laser direct imaging. However, unlike inner layers that are typically negative images, the outer layer imaging will be done with positive images. This is necessary as the circuit image on the photoresist is developed away, leaving the circuit copper exposed for plating. Major PCB design tools allow you to define unique constrained areas within a PCB. A prime example is for BGAs, where you will want to have different, and much tighter, rules in place than apply to the rest of the PCB. Your DfM software should have the ability to read these CAD constrained maps. That saves the user from having to manually review all “false” DfM issues caused by using the general PCB rules within this constrained area. A common rule violation on outer layers is called a “same net sliver,” as seen in Figure 4. And while electrically correct, they present significant difficulty to the PCB fabricator. In a case like this, the width of the photo-resist (as shown in black) is so thin it runs the risk of breaking and then re-depositing elsewhere on the board, potentially causing a short or an open. With today’s strict and low tolerance constraints for high speed nets, a same net sliver could shorten the connection and significantly change the impedance of the circuit. <b> Auxiliary Processes </b> Two important processes at this point are the application of solder mask and silk screen. Typical soldermask checks include rules governing how close lines can pass to a pad and how close two pads can be. Lines that pass close to a pad must be fully covered by mask to avoid solder bridging between the line and pad during the soldering process. Once again, if we consider process tolerances, the application of photo-imageable soldermask has a positional tolerance of +/- 3 mils or .08 mm. It’s important to assure that you have at least this much clearance around your soldermask pads. DfM can also identify a very small sliver of soldermask between two pads. If a piece of mask detaches, the defect is typically a bad solder joint as the mask debris gets embedded in the solder. This can lead to a bad connection or even an open depending on the size of the mask fragment compared to the size of the solder joint. Below a minimum web width of around 0.1 mm, the fabricator will be forced to use a gang solder mask. These issues may not be identified at the design stage because many designers follow IPC’s recommendation to create soldermask 1:1 with the pad. The idea is the fabricator will add the necessary growth to the soldermask for their processes. However, by ignoring this at the design stage, you are running the risk that these soldermask issues, once found by your fabricator, will cause a delay as you have to either change the layout or approve the use of a gang mask. Silkscreen can also cause problems. Silkscreen should never be applied on pads since it is considered a contaminant to the solder and will prevent a quality solder joint. If the defined silkscreen uses a stroke size too small for the screen printer to actually image, it is likely too small to serve its purpose. In this event, the fabricator will ask the designer’s permission to either increase the line width or to remove it from the legend. Although this may not be considered a fatal error, it is another potential cause for delay in the fabrication process. <b> De-Panelization </b> The final step before test is to separate the panels into individual PCBs and make all internal cutouts or routs. Here the design must maintain a minimum copper setback from board or slot edges to avoid damaging the circuits. Keep in mind that most CNC routing is going to have a mechanical tolerance of +/- 10 mils or .25 mm. <b> Test and Inspection </b> The PCB fabrication process finishes by subjecting the boards to electrical test, which unfortunately, is where many issues actually get caught if the designer has not implemented good DfM verification practices during the design process. Testing may be done with a flying probe or flying grid tester for low volumes or with a bed-of-nails tester for higher volumes. <b> Summary </b> This article presented a quick and very cursory step through the PCB fabrication process, pointing out just a few of the many issues that can affect bare board manufacturing costs and yields. The more you are aware of your fabricator’s perspective, the fewer issues you will have once you release your design to manufacturing. The key is not to wait until your fabricator discovers these problems but to use DfM verification software during the design process so that your fabricator will be just as happy with your design as you and your layout tool are.
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